1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a reset circuit for generating a reset signal by using a self-bias circuit regardless of a power-up slope only when a power voltage is beyond a predetermined voltage, and a nonvolatile ferroelectric memory device using the same.
2. Description of the Prior Art
Generally, a FeRAM has the same data processing speed as a dynamic random access memory (DRAM) and retains data even when power is off. For this characteristic, the FeRAM has been highly attracted as a next generation memory device.
The FeRAM has structures similar to those of a DRAM, and uses ferroelectric material as a component of a capacitor. The FeRAM uses a characteristic of high residual polarization in ferroelectric material.
Due to the high residual polarization, data remains unerased even if the electric field is removed.
FIG. 1 illustrates a hysteresis loop of a general ferroelectric.
As shown in FIG. 1, polarization induced by the electric field is maintained at a certain amount (i.e., “d” and “a” states) due to the presence of residual polarization (or spontaneous polarization), even if the electric field is removed.
A FeRAM cell may be used as a memory device by corresponding the “d” and “a” states to 1 and 0, respectively.
FIG. 2 illustrates a unit cell of a conventional FeRAM device.
As shown in FIG. 2, the unit cell of the conventional FeRAM device includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline B/L and a plateline P/L arranged parallel to the wordline and spaced at a predetermined interval from the wordline W/L. The unit cell also includes a NMOS transistor having a gate connected to the wordline W/L and a source connected to the bitline B/L, and a ferroelectric capacitor FC1 connected between a drain of the NMOS transistor and the plateline P/L.
The data input/output operation of the conventional FeRAM device is now described as follows.
FIG. 3A is a timing chart illustrating a write mode operation of a general FeRAM device, and FIG. 3B is a timing chart illustrating a read mode operation of a general FeRAM device.
Referring to FIG. 3A, if an externally applied chip enable signal CSBPAD is activated from ‘high’ to ‘low’, a write enable signal is transited from ‘high’ to ‘low’, and the writing mode starts.
Subsequently, if an operation of decoding addresses starts in the write mode, the corresponding wordline W/L transits from ‘low’ to ‘high’ to select the cell.
During the interval wherein the wordline W/L maintains a ‘high’ state, a ‘high’ signal of a predetermined period and a ‘low’ signal of a predetermined period are alternatively applied to a corresponding plateline P/L. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronous with respect to the write enable signal WEBPAD are applied to a corresponding bitline B/L.
As shown in the following Table 1, during the period wherein a ‘high’ signal is applied to a wordline W/L, if a ‘high’ signal is applied to the bitline B/L and a ‘low’ signal is applied to the plateline P/L, a logic value ‘1’ is written in the ferroelectric capacitor FC1. If a ‘low’ signal is applied to the bitline B/L and a ‘high’ signal is applied to the plateline P/L, a logic value ‘0’ is written in the ferroelectric capacitor FC1.
TABLE 1P/LW/L:HHLB/LHX1L0XReferring to FIG. 3B, If an externally applied chip enable signal CSBPAD is activated from ‘high’ to ‘low’, all of the bitlines become equipotential to low voltage by an equalizer signal before a corresponding wordline is selected.
Then, after each bitline becomes inactive, an address is decoded. A wordline corresponding to the decoded address is transited from the low to the high level, to enable a selected cell.
A ‘high’ signal is applied to a corresponding plateline of the selected cell to destroy a data Qs corresponding to a logic value ‘1’ stored in the ferroelectric memory cell. If a logic value ‘0’ is stored in the ferroelectric memory cell, its corresponding data Qns is not destroyed.
The destroyed data or the non-destroyed data is outputted to bitlines, according to the above-described hysteresis loop characteristics, so that a sense amplifier senses logic values ‘1’ or ‘0’.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. The logic value ‘1’ is output in case the data is destroyed, while the logic value ‘0’ is output in case the data is not destroyed.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, the plateline P/L becomes inactive from ‘high’ to ‘low’ during the interval where the ‘high’ signal is applied to the corresponding wordline W/L.
In a system using a nonvolatile FeRAM as a memory device, a system controller outputs a chip enable signal CSBPAD into a FeRAM chip. A memory device in the memory chip such as a FeRAM chip generates a chip internal control signal CE for operating a memory cell of a chip according to the chip enable signal CSBPAD. Data is read or written according to the chip internal control signal CE. The data is transferred to the system controller via a data bus.
The system is re-setup by reading data stored in a code register, when a power is applied to the nonvolatile FeRAM. The code register reading operation is performed using a power-on reset signal.
A conventional power-on reset signal generating circuit is configured to have much influence on generation of a reset signal by a power-on slope of a voltage. As a result, the reset signal is generated even in a low power voltage if the power-on slope becomes longer.
FIG. 4 is a circuit diagram showing a conventional power-on reset circuit.
The conventional power-on reset circuit of FIG. 4 comprises a PMOS transistor T1 and a NMOS capacitor T2 connected in series between a power voltage VCC and a ground voltage VSS and a gate of the PMOS transistor T1 is connected to the ground voltage VSS. The power-on reset circuit further comprises a first inverter INV1, a second inverter INV2, a PMOS transistor T3 and a third inverter INV3. The first inverter INV1 inverts an output voltage of the PMOS transistor T1. The second inverter INV2 inverts an output signal of the first inverter INV1. The PMOS transistor T3 is controlled by an output signal of the second inverter INV2, and connected between the power voltage VCC and an output terminal of the first inverter INV1. The third inverter INV3 inverts an output signal of the second inverter INV2, and outputs a reset signal.
Levels of output voltages in the power-on reset circuit are determined by a RC delay time between the PMOS transistor T1 serving as a current source and the NMOS transistor T2 serving as a capacitor device.
The power-up operation should be performed in a predetermined time for the stable operation of the memory chip. However, if the power-up time is over the predetermined time by a certain factor, data stored in the code register is destroyed.
FIGS. 5 and 6 are waveform diagrams showing the operation of the power-on reset circuit of FIG. 4, respectively, when the power voltage increases with a fast gradient and when the power voltage increases with a slow gradient.
As shown in FIG. 5, when the power voltage increases rapidly from the VSS level(ground) to the VCC level with the fast gradient, a reset signal is generated at a voltage higher than a predetermined voltage level (threshold voltage).
Referring to FIG. 6, when the power voltage increases slowly from the VSS level to the VCC level with the slow gradient, the NMOS capacitor T2 is precharged for more time than the case of FIG. 5, thereby rapidly increasing a sensing level of the NMOS capacitor T2. As a result, a reset signal is generated at a voltage lower than the threshold voltage.
As described above, in the conventional power-on reset circuit, the reset signal may be generated at a voltage lower than a normal voltage because of unstable generation of the power-on reset signal according to variations of the power. If the code register is operated at a low voltage, data stored in the code register is mis-read or restored in an insufficient state, thereby causing failure in the code register.
Accordingly, a reset circuit configured to generate a power-on reset signal beyond a predetermined voltage in any power-on slope is required.